/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023.
 * Description: define some cache operation for hardware bug
 * Author: Abbott Liu <liuwenliang@huawei.com>
 * Create: 2023-09-06
 */

#ifndef __ARCH_HI138X_CACHE_OPS_H__
#define __ARCH_HI138X_CACHE_OPS_H__

#ifdef CONFIG_CORTEX_A15
static inline void fix_flush_tlb_bug_for_1381(void)
{
	/* Add this Code to fix flush tlb bug in 1381 */
	asm("mcr p15, 0, %0, c8, c6, 0" : : "r"(0) : "cc");     /* Invalidate entire TLB Inner Shareable */
	asm("mcr p15, 0, %0, c8, c3, 0" : : "r"(0) : "cc");     /* Invalidate data TLB */
}
#else
static inline void fix_flush_tlb_bug_for_1381(void) { }
#endif

#endif
